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www.irf.com 14-aug-09 ? 2009 international rectifier 1 half-bridge gate driver ic features ? floating channel up to 600 v or 1200 v ? soft over-current shutdown ? synchronization signal to synchronize shutdown wit h the other phases ? integrated desaturation detection circuit ? two stage turn on output for di/dt control ? separate pull-up/pull-down output drive pins ? matched delay outputs ? undervoltage lockout with hysteresis band ? lead free description the ir2114/ir2214 gate driver family is suited to d rive a single half bridge in power switching applications. these drivers provide high gate driving capability (2 a source, 3 a sink) and require low q uiescent current, which allows the use of bootstrap power supply techniques in medium power systems. these drivers feature full short circuit p rotection by means of power transistor desaturation detection and manage all ha lf-bridge faults by smoothly turning off the desaturated transistor thr ough the dedicated soft shutdown pin, therefore preventing over-voltages an d reducing electromagnetic emissions. in multi-phase systems, the ir2114/ir2214 drivers communicate using a dedicated local network (sy_flt and fault/sd signals) to properly manage phase-to-phase short circuits. the system controller may force shutdown or read device fault state through the 3.3 v compatible cmos i/o pin (fault/sd). to improv e the signal immunity from dc-bus noise, the control and power ground use dedicated pins enabling low-side emitter current sensing as well. undervoltage conditions in floating and low voltage circuits are managed indep endently. product summary v offset 600 v or 1200 v max. i o +/- (min) 1.0 a / 1.5 a v out 10.4 v ? 20 v deadtime matching (max) 75 ns deadtime (typ) 330 ns desat blanking time (typ) 3 s dsh, dsl input voltage threshold (typ) 8.0 v soft shutdown time (typ) 9.25 s package 24-lead ssop typical connection ir2114sspbf/IR2214SSPBF data sheet no. pd60213 r evl
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 2 recommended operating conditions for proper operation the devi ce should be used within the recommended conditions . all voltage parameters are absolute voltages referenced to v ss . the v s offset rating is tested with all supplies biased a t a 15 v differential. symbol definition min. max. units v b high side floating supply voltage ? v s + 11.5 v s + 20 ir2114 v ss 600 v s high side floating supply offset voltage ?? ir2214 v ss 1200 v ho high side output voltage (hop, hon and ssdh) v s v s + 20 v lo low side output voltage (lop, lon and ssdl) v com v cc v cc low side and logic fixed supply voltage (note 1) 1 1.5 20 com power ground -5 5 v in logic input voltage (hin, lin and flt_clr) v ss v cc v flt fault input/output voltage (fault/sd and sy_flt) v ss v cc v dsh high side ds pin input voltage v s - 2.0 v b v dsl low side ds pin input voltage v com - 2.0 v cc v t pwhin high side pulse width for hin input 1 s t a ambient temperature -40 125 c ? while internal circuitry is operational below the indicated supply voltages, the uv lockout disables the output drivers if the uv thresholds are not reached. a min imum supply voltage of 8v is recommended for the dr iver to operate safely under switching conditions at vs pin (please refer to the ?start-up sequence? in app lication section of this document) ?? logic operational for v s from v ss -5 v to v ss +600 v or 1200 v. logic state held for v s from v ss -5 v to v ss - v bs . for a negative spike on v b (referenced to v ss ) of less than 200ns the ic will withstand a sustai ned peak of -40v under normal operation and an isolated even t of up to -70v peak spike (please refer to the des ign tip dt97-3 for more details). absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltage parameters are absolute voltages referenced to v ss , all currents are defined positive into any lead t he thermal resistance and power dissipation ratings are measured under bo ard mounted and still air conditions. symbol definition min. max. units v s high side offset voltage v b - 25 v b + 0.3 ir2114 -0.3 625 v b high side floating supply voltage ir2214 -0.3 1225 v ho high side floating output voltage (hop, hon and ss dh) v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 com power ground v cc - 25 v cc + 0.3 v lo low side output voltage (lop, lon and ssdl) v com -0.3 v cc + 0.3 v in logic input voltage (hin, lin and flt_clr) -0.3 v cc + 0.3 v flt fault input/output voltage (fault/sd and sy_flt) -0.3 v cc + 0.3 v dsh high side ds input voltage v s -3 v b + 0.3 v dsl low side ds input voltage v com -3 v cc + 0.3 v dvs/dt allowable offset voltage slew rate ? 50 v/ns p d package power dissipation @ t a 25 c ? 1.5 w rth ja thermal resistance, junction to ambient ? 65 c/w t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 3 static electrical characteristics v cc = 15 v, v ss = com = 0 v, v s = 600 v or 1200 v and t a = 25 c unless otherwise specified. pins: v cc , v ss , v b , v s (refer to fig. 1) symbol definition min typ max units test conditions v ccuv+ v cc supply undervoltage positive going threshold 9.3 1 0.2 11.4 v ccuv- v cc supply undervoltage negative going threshold 8.7 9 .3 10.3 v ccuvh v cc supply undervoltage lockout hysteresis ? 0.9 ? v bsuv+ (v b -v s ) supply undervoltage positive going threshold 9.3 10.2 11.4 v bsuv- (v b -v s ) supply undervoltage negative going threshold 8.7 9.3 10.3 v s = 0 v, v s = 600 v or 1200 v v bsuvh (v b -v s ) supply undervoltage lockout hysteresis ? 0.9 ? v i lk offset supply leakage current ? ? 50 v b = v s = 600 v or 1200 v i qbs quiescent v bs supply current ? 400 800 a v in = 0 v or 3.3 v i qcc quiescent v cc supply current ? 0.7 2.5 ma no load pins: hin, lin, fltclr, fault/sd, sy_flt (refer to fig. 2, 3) symbol definition min typ max units test conditions v ih logic "1" input voltage 2.0 ? ? v il logic "0" input voltage ? ? 0.8 v ihss logic input hysteresis 0.2 0.4 ? v v cc = v ccuv- to 20 v logic ?1? input bias current (hin, lin, fltclr) ? 3 30 ? i in+ logic ?0? input bias current (fault/sd, sy_flt) 0 ? 1 v in = 3.3 v logic ?0? input bias current -1 ? 0 i in- logic ?1? input bias current (fault/sd, sy_flt) -1 ? 0 a v in = 0 v r on,flt fault/sd open drain resistance ? 60 ? r on,sy sy_flt open drain resistance ? 60 ? pw 7 s pins: dsl, dsh (refer to fig. 4) v desat , i ds and i dsb parameters are referenced to com and v s respectively for dsl and dsh. symbol definition min typ max units test conditions v desat+ high desat input threshold voltage 7.2 8.0 8.8 v desat- low desat input threshold voltage 6.3 7.0 7.7 v dsth desat input voltage hysteresis ? 1.0 ? v see figs. 4,16 i ds+ high dsh or dsl input bias current ? 21 ? v desat = v cc or v bs i ds - low dsh or dsl input bias current ? -160 ? a v desat = 0 v
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 4 pins: hop, lop (refer to fig. 5) symbol definition min typ max units test conditions v oh high level output voltage, v b ? v hop or v cc ?v lop ? 40 300 mv i o = 20 ma i o1+ output high first stage short circuit pulsed curre nt 1 2 ? v hop/lop = 0 v, h in or l in = 1, pw 200 ns, resistive load, see fig. 8 i o2+ output high second stage short circuit pulsed curre nt 0.5 1 ? a v hop/lop = 0 v, h in or l in = 1, 400 ns pw 10 s, resistive load, see fig. 8 pins: hon, lon, ssdh, ssdl (refer to fig. 6) symbol definition min typ max units test conditions v ol low level output voltage, v hon or v lon ? 45 300 mv i o = 20 ma r on,ssd soft shutdown on resistance ? ? 90 ? pw 7 s i o- output low short circuit pulsed current 1.5 3 ? a v hop/lop = 15 v, h in or l in = 0, pw 10 s ? ssd operation only
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 5 ac electrical characteristics v cc = v bs = 15 v, v s = v ss and t a = 25 c unless otherwise specified. symbol definition min. typ. max. units test conditions t on turn on propagation delay 220 440 660 t off turn off propagation delay 220 440 660 t r turn on rise time (c load =1 nf) ? 24 ? t f turn off fall time (c load =1 nf) ? 7 ? v in = 0 & 1, v s = 0 v to 600 v or 1200 v, hop shorted to hon, lop shorted to lon, fig. 7 t on1 turn on first stage duration time 120 200 280 fig. 8 t desat1 dsh to ho soft shutdown propagation delay at ho turn on 2000 3300 4600 v hin = 1 v t desat2 dsh to ho soft shutdown propagation delay after blanking 1050 ? ? v desat = 15 v, fig. 10 t desat3 dsl to lo soft shutdown propagation delay at lo turn on 2000 3300 4600 v lin = 1 v t desat4 dsl to lo soft shutdown propagation delay after blanking 1050 ? ? v desat = 15 v, fig. 10 t ds soft shutdown minimum pulse width of desat 1000 ? ? fig. 9 t ss soft shutdown duration period 5700 9250 13500 v ds =15 v, fig. 9 t sy_flt, desat1 dsh to sy_flt propagation delay at ho turn on ? 3600 ? v hin = 1 v t sy_flt, desat2 dsh to sy_flt propagation delay after blanking 1300 ? ? v ds = 15 v, fig. 10 t sy_flt , desat3 dsl to sy_flt propagation delay at lo turn on ? 3050 ? v lin = 1 v t sy_flt , desat4 dsl to sy_flt propagation delay after blanking 1050 ? ? v desat =15 v, fig. 10 t bl ds blanking time at turn on ? 3000 ? v hin = v lin = 1 v, v desat =15 v, fig. 10 deadtime/delay matching characteristics dt deadtime ? 330 ? fig. 11 mdt deadtime matching, mdt=dth-dtl ? ? 75 external dt = 0 s, fig. 11 pdm propagation delay matching, max (ton, toff) ? min (ton, toff) ? ? 75 ns external dt > 500 ns, fig. 7
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 6 figure 1: undervoltage diagram figure 2: hin, lin and fltclr diagram figure 3: fault/sd and sy_flt diagram figure 4: dsh and dsl diagram figure 5: hop and lop diagram figure 6: hon, lon, ssdh and ssdl diagram v cc /v b v ccuv /v bsuv v ss /v s comparator uv internal signal hin/lin/ fltclr v ss schmitt trigger 10k internal signal lop/hop v cc /v b on/off internal signal v oh 200ns oneshot ssdl/ssdh com/v s on/off internal signal r on,ssd lon/hon desat internal signal v ol dsl/dsh v desat com/v s comparator 100k 700k v cc /v bs ssd internal signal fault/sd sy_flt v ss schmitt trigger r on fault/hold internal signal
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 7 hin lin ho (hop=hon) lo (lop=lon) 10% 3.3v pw in pw out 10% 90% 90% 50% 50% t on t r t off t f figure 7: switching time waveforms ton1 io1+ io2+ figure 8: output source current hin/lin ho/lo 8v 8v t ss t desat 3.3v dsh/dsl t ds ssd driver enable figure 9: soft shutdown timing waveform
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 8 hin dsh sy_flt t desat1 8v 50% t sy_flt,desat1 hon 90% 50% t bl fault/sd fltclr softshutdown lin lon 90% softshutdown t desat2 8v t sy_flt,desat2 50% t bl dsl 90% 50% t bl softshutdown 90% softshutdown 50% t bl 8v 8v 50% t sy_flt,desat3 t sy_flt,desat4 t desat3 t desat4 50% 50% turn-on propagation delay turn-on propagation delay 90% turn_off propagation delay 50% 90% 50% 50% 10% 10% figure 10: desat timing hin lin ho (hop=hon) lo (lop=lon) dth dtl 50% 50% 50% 50% 50% 50% mdt=dth-dtl figure 11: internal deadtime timing
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 9 lead assignments 24-lead ssop lead definitions symbol description v cc low side gate driver supply v ss logic ground hin logic input for high side gate driver outputs ( hop/hon) lin logic input for low side gate driver outputs (l op/lon) fault/sd dual function (in/out) active low pin. refer to figs . 15, 17, and 18. as an output, indicates fault con dition. as an input, shuts down the outputs of the gate dri ver regardless h in /l in status. sy_flt dual function (in/out) active low pin. refer to figs . 15, 17, and 18. as an output, indicates ssd seque nce is occurring. as an input, an active low signal fre ezes both output status. flt_clr fault clear active high input. clears latche d fault condition (see fig. 17) lop low side driver sourcing output lon low side driver sinking output dsl low side igbt desaturation protection input ssdl low side soft shutdown com low side driver return v b high side gate driver floating supply hop high side driver sourcing output hon high side driver sinking output dsh high side igbt desaturation protection input ssdh high side soft shutdown v s high side floating supply return ssop24 1 12 24 13 ssdl flt_clr hin com sy_flt lon fault/sd vss lop vcc dsl hop ssdh hon n.c. vs n.c. dsh vb n.c. n.c. n.c. n.c. lin
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 10 schmitt trigger input shoot through prevention (dt) deadtime level shifters latch local desat protection soft shutdown uv_vbs detect di/dt control driver uv_vcc detect local desat protection softshutdown di/dt control driver on/off on/off desat soft shutdown on/off soft shutdown on/off (hs) desaths desatls on/off (ls) hard shutdown internal hold sd fault logic managemend (see figure 14) uv_vcc vb hop hon ssdh dsh vs lop lon ssdl dsl com vss flt_clr fault/sd sy_flt lin hin vcc fault hold ssd input hold logic output shutdown logic functional block diagram start-up sequence fault ho/lo=1 ho=lo=0 undervoltage v cc ho=lo=0 freeze shutdown s y _ f l t s y _ f l t s y _ f l t f l t _ c l r h i n / l i n h i n / l i n u v _ v c c u v _ v c c uv_vbs f a u l t / s d d s h / l d s h / l f a u l t / s d f a u l t / s d f a u l t / s d f a u l t / s d u v _ v b s uv_vcc desat event undervoltage v bs ho=0, lo=lin soft shutdown state diagram stable state ? fault ? ho=lo=0 (normal operation) ? ho/lo=1 (normal operation) ? undervoltage v cc ? shutdown (sd) ? undervoltage v bs ? freeze temporary state ? soft shutdown ? start up sequence system variable ? flt_clr ? hin/lin ? uv_vcc ? uv_vbs ? dsh/l ? sy_flt ? fault/sd note 1: a change of logic value of the signal labele d on lines (system variable) generates a state tran sition. note 2: exiting from undervoltage v bs state, the ho goes high only if a rising edge even t happens in h in .
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 11 ho/lo status hop/lop hon/lon ssdh/ssdl 0 hiz 0 hiz 1 1 hiz hiz ssd hiz hiz 0 lo/ho output follows inputs (in=1->out=1, in=0->out=0) lo n-1 /ho n-1 output keeps previous status logic table: output drivers status description inputs input/output undervoltage yes: v< uv threshold no : v> uv threshold x: don?t care outputs operation hin lin flt_clr ______ sy_flt ssd: desat (out) hold: freezing (in) _________ fault/sd sd: shutdown (in) fault: diagnostic (out) v cc v bs ho lo shutdown x x x x 0 (sd) x x 0 0 fault clear h in l in x ? (fault) no no ho lo fault cleared h in l in 1 x 1 ?? no no ho lo 1 0 0 1 1 no no 1 0 0 1 0 1 1 no no 0 1 normal operation 0 0 0 1 1 no no 0 0 anti shoot through 1 1 0 1 1 no no 0 0 1 0 0 (ssd) 1 no no ssd 0 soft shutdown (entering) 0 1 0 (ssd) 1 no no 0 ssd x x 0 (ssd) (fault) no no 0 0 soft shutdown (finishing) x x 0 (ssd) (fault) no no 0 0 freeze x x x 0 (hold) 1 no no ho n-1 lo n-1 x l in x 1 1 no yes 0 lo undervoltage x x x 1 0 (fault) yes x 0 0 ? sy_flt automatically resets after the ssd event is over, without requiring flt_clr to be asserted. to avoid flt_clr conflicting with the ssd sequence of o perations, in the event of a ssd during normal operation it is recommended not to apply flt_clr whi le sy_flt is active. at power supply start-up instead, it is recommended to keep flt_clr active to prevent spurious diagnostic signals being generated, as described in section 1.1 start-up seq uence and in section 1.4.5 fault management at start-up. ?? holding flt_clr high all time will not allow the gate driver to latch the fault status and migth compromise power system protection.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 12 1 features description 1.1 start-up sequence at power supply start-up, it is recommended to keep the flt_clr pin active until the supply voltages are properly established. this prevents spurious diagno stic signals being generated. when the bootstrap supply topology is used for supplying the floating high side stage, the followi ng start- up sequence is recommended (see also fig. 12): 1. set v cc , 2. set flt_clr pin to high level, 3. set lin pin to high level and charge the bootstrap capacitor, 4. release lin pin to low level, 5. release flt_clr pin to low level. vcc flt_clr lin lo figure 12 start-up sequence a minimum 15 s lin and flt-clr pulse is required. a minimum supply voltage of 8v is recommended for t he driver to operate safely under switching conditions at vs pin. at lower supply the gate driving capability de creases and might become not sufficient to counteract switc hing charge injected to the outputs. 1.2 normal operation mode after the start-up sequence has completed, the devi ce becomes fully operative (see grey blocks in the sta te diagram). hin and lin produce driver outputs to switch accordingly, while the input logic monitors the inp ut signals and deadtime (dt) prevent shoot-through even ts from occurring. 1.3 shutdown the system controller can asynchronously command the hard shutdown (hsd) through the 3.3 v compatible cmos i/o fault/sd pin. this event is not latched. in a multi-phase system, fault/sd signals are or-ed s o the controller or one of the gate drivers can force the simultaneous shutdown of the other gate drivers thr ough the same pin. 1.4 fault management the ir2114/ir2214 is able to manage supply failure (undervoltage lockout) and transistor desaturation (on both the low and high side switches). 1.4.1 undervoltage (uv) the undervoltage protection function disables the driver?s output stage which prevents the power devi ce from being driven when the input voltage is less th an the undervoltage threshold. both the low side (v cc supplied) and the floating side (v bs supplied) are controlled by a dedicate undervoltage function. an undervoltage event on the v cc pin (when v cc < uv vcc- ) generates a diagnostic signal by forcing the fault/sd pin low (see fault/sd section and fig. 14). this event disables both the low side and floa ting drivers and the diagnostic signal holds until the undervoltage condition is over. the fault condition is not latched and the fault/sd pin is released once v cc becomes higher than uv vcc+ . the v bs undervoltage protection works by disabling only the floating driver. undervoltage on v bs does not prevent the low side driver from activating its output nor does it generate diagnostic signals. the v bs undervoltage condition (v bs < uv vbs- ) latches the high side output stage in the low state. v bs must exceed the uv vbs+ threshold to return the device to its normal operat ing mode. to turn on the floating driver, h in must be re- asserted high (rising edge event on h in is required). 1.4.2 power devices desaturation different causes can generate a power inverter fail ure (phase and/or rail supply short-circuit, overload conditions induced by the load, etc.). in all of th ese fault conditions, a large increase in current results in the igbt. the ir2114/ir2214 fault detection circuit monitors t he igbt emitter to collector voltage (v ce ) (an external high voltage diode is connected between the igbt?s collec tor and the ics dsh or dsl pins). a high current in the igbt may cause the transistor to desaturate; this condition results in an increase of v ce . once in desaturation, the current in the power tran sistor can be as high as 10 times the nominal current. whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltage). the gate driver is ab le to control the transient condition by smoothly turning off the desaturated transistor with its integrated soft shu tdown (ssd) protection. 1.4.3 desaturation detection: dsh/l function figure 13 shows the structure of the desaturation sensing and soft shutdown block. this configuration is the same for both the high and low side output stag es.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 13 ron,ss rdsh/l figure 13: high and low side output stage fltclr q q set clr s r fault/sd sy_flt internal hold (external hold) (external hard shutdown) internal fault (hard shutdown) uvcc desaths desatls figure 14: fault management diagram the external sensing diode should have breakdown voltage greater than 600 v (ir2114) or 1200 v (ir22 14), low stray capacitance and low recovery current (in order to minimize noise coupling and switching delays). i n series an external decoupling 1k resistor is required in order to limit the current flowing in and out of ds h and dsl pins because of switching noise coupled through the external de-saturation sensing diode. the diode is biased by an internal pull-up resistor r dsh/l (equal to v cc /i ds- or v bs /i ds- ). when v ce increases, the voltage at the dsh or dsl pin increases too. being internally biased to the local supply, the dsh/dsl voltage is automatically clamped. when dsh/dsl exceeds the v desat+ threshold, the comparator triggers (see fig. 13). the comparator?s output is filtered in order to avoi d false desaturation detection by externally induced noise; pulses shorter than t ds are filtered out. to avoid detecting a false desaturation event during igbt tu rn on, the desaturation circuit is disabled by a blanking signal (t bl , see blanking block in fig. 13). this time is the estimated maximum igbt turn on time and must be not exceeded by proper gate resistance sizing. when the igbt is not completely saturated after t bl , desaturation is detected and the driver will turn off. eligible desaturation signals initiate the ssd sequ ence. while in ssd, the driver?s output goes to a high impedance state and the ssd pull-down is activated to turn off the igbt through the ssdh/ssdl pin. the sy_flt output pin (active low, see fig. 14) reports t he gate driver status during the ssd sequence (t ss ). once the ssd has finished, sy_flt releases, and the gate driver generates a fault signal (see the fault/sd section) by activating the fault/sd pin. this generate s a hard shutdown for both the high and low output st ages (ho=lo=low). each driver is latched low until the f ault is cleared (see flt_clr). figure 14 shows the fault management circuit. in thi s diagram desaths and desatls are two internal signal s that come from the output stages (see fig. 13). it must be noted that while in ssd, both the undervoltage fault and external sd are masked until the end of ssd. desaturation protection is working independently by the other control pin and it is di sabled only when the output status is off. for the purpose of sensing the power transistor desaturation, the collector voltage is monitored (a n external high voltage diode is connected between th e igbt?s collector and the ic?s dsh or dsl pin). the diode is normally biased by an internal pull up res istor connected to the local supply line (v b or v cc ). when the transistor is ?on? the diode is conducting and the amount
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 14 of current flowing in the circuit is determined by the internal pull up resistor value. in the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see fig. 19). in fact, a pull up resistor with a low resistance may result in a high current the significantly discharges the bootstrap capacitor. fo r that reason, the internal pull up resistor typical value is of the order of 100 k . while the impedance of the dsh/dsl pins is very low when the transistor is on (low impedance path throu gh the external diode down to the power transistor), t he impedance is only controlled by the pull up resisto r when the transistor is off. in that case, relevant dv/dt generated at vs node might push the dsh/dsl pins outside the recommended operating conditions. 1.4.4 fault management in multi-phase systems in a system with two or more gate drivers the ir2114/ir2214 devices must be connected as shown in fig. 15. vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 phase u phase v phase w fault figure 15: ir2214 used in a 3 phase application sy_flt: the bi-directional sy_flt pins communicate each other through a local network. the logic signal is active low. the device that detects the igbt desaturation activates the sy_flt, which is then read by the other gate drivers. when sy_flt is active all the drivers hold their output state regardless of the i nput signals (h in , l in ) they receive from the controller (freeze state). this feature is particularly important in p hase-to- phase short circuit where two igbts are involved; i n fact, while one is softly shutting-down, the other must be prevented from hard shutdown to avoid exiting ssd. in the freeze state, the frozen drivers are not comple tely inactive because desaturation detection still takes the highest priority. sy_flt communication has been designed for creating a local network between the drivers. there is no need to wire sy_flt to the controller. fault/sd: the bi-directional fault/sd pins communicate with each other and with the system controller. the logic signal is active low. when low , the fault/sd signal commands the outputs to go off by hard shutdown. there are three events that can forc e fault/sd low: 1. desaturation detection event: the fault/sd pin is latched low when ssd is over, and only a flt_clr signal can reset it; 2. undervoltage on v cc : the fault/sd pin is forced low and held until the undervoltage is active. this event is not latched; 3. fault/sd is externally driven low either from the controller or from another ir2114/ir2214 device. this event is not latched; therefore the flt_clr cannot disable it. only when fault/sd becomes high the device returns to its normal operating mode. 1.4.5 fault management at start-up when the bootstrap supply topology is used for supplying the floating high side and the recommende d power supply start-up sequence is followed, flt_clr pin must be kept active to prevent spurious diagnos tic signals being generated. in the event of power inverter failure already pres ent or occurring during start-up (phase and/or rail supply short- circuit, overload conditions induced by the load, e tc.), keeping the flt_clr pin active will also prevent the real fault condition to be detected with the fault/sd pin. in such a condition a large current increase i n the igbt will desaturate the transistor, allowing the g ate driver to detect and turn-off the desaturated trans istor with the integrated soft shutdown (ssd) protection. as with a normal ssd sequence, during ssd the sy_flt output pin (active low, see fig. 14) will repor t the gate driver status. but now, being the flt_clr pi n already active, the gate driver will not generate a fault signal by activating the fault/sd pin and it will no t enter hard shutdown. to prevent the driver to resume charging the bootstr ap capacitor, therefore re-establishing the condition that will determine again the occurrence of the large current increase in the igbt, it is recommended to monitor the sy_flt output pin. should the sy_flt output pin go low during the start-up sequence, the controller mu st interpret a power inverter failure is present, and stop the start-up sequence. 1.6 output stage the structure is shown in fig. 13 and consists of two turn on stages and one turn off stage. when the dri ver turns on the igbt (see fig. 8), a first stage is act ivated while an additional stage is maintained in the acti ve state for a limited time (t on1 ). this feature boosts the total driving capability in order to accommodate both a f ast gate charge to the plateau voltage and dv/dt contro l in switching. at turn off, a single n-channel sinks up to 3 a (i o- ) and offers a low impedance path to prevent the self-tur n on due to the parasitic miller capacitance in the powe r switch. 1.7 timing and logic state diagrams description the following figures show the input/output logic diagram. figure 17 shows the sy_flt and fault/sd signals as outputs, whereas fig. 18 shows them as inputs.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 15 hin lin fault/sd lo(lop/lon) dsh flt_clr sy_flt ho(hop/hon) dsl a b c d e f g figure 17: i/o timing diagram with sy_flt and fault/sd as output a b c d e f hin lin sy_flt fault/sd flt_clr ho (hop/hon) lo (lop/lon) figure 18: i/o logic diagram with sy_flt and fault/sd as input referred to the timing diagram of fig. 17: a. when the input signals are on together the outputs go off (anti-shoot through), b. the ho signal is on and the high side igbt desaturates, the ho turn off softly while the sy_flt stays low. when sy_flt goes high the fault/sd goes low. while in ssd, if lin goes up, lo does not change (freeze), c. when fault/sd is latched low (see fault/sd section) flt_clr can disable it and the outputs go back to follow the inputs, d. the dsh goes high but this is not read because ho is off, e. the lo signal is on and the low side igbt desaturates, the low side behaviour is the same as described in point b, f. the dsl goes high but this is not read as lo is off, g. as point a (anti-shoot through ). referred to the timing diagram fig. 18: a. the device is in the hold state, regardless of input variations. the hold state results as sy_flt is forced low externally, b. the device outputs go off by hard shutdown, externally commanded. a through b is the same sequence adopted by another ir2x14x device in ssd procedure. c. externally driven low fault/sd (shutdown state) cannot be disabled by forcing flt_clr (see fault/sd section), d. the fault/sd is released and the outputs go back to follow the inputs, e. externally driven low fault/sd: outputs go off by hard shutdown (like point b), f. as point a and b but for the low side output.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 16 2 sizing tips 2.1 bootstrap supply the v bs voltage provides the supply to the high side driver circuitry of the gate driver. this supply sit s on top of the v s voltage and so it must be floating. the bootstrap method is used to generate the v bs supply and can be used with any of the ir211(4,41)/ ir221(4,41) drivers. the bootstrap supply is formed by a diode and a capacitor as connected in fig. 19. bootstrap diode ir2214 bootstrap capacitor vb vs vcc hop hon ssdh dc+ bootstrap resistor com v cc v bs v f v ge v ceon v fp i load motor r boot figure 19: bootstrap supply schematic this method has the advantage of being simple and lo w cost but may force some limitations on duty-cycle a nd on-time since they are limited by the requirement t o refresh the charge in the bootstrap capacitor. prop er capacitor choice can reduce drastically these limitations. 2.2 bootstrap capacitor sizing to size the bootstrap capacitor, the first step is t o establish the minimum voltage drop ( ? v bs ) that we have to guarantee when the high side igbt is on. if v gemin is the minimum gate emitter voltage we want to maintain, the voltage drop must be: ceon ge f cc bs v v v v v ? ? ? ? min under the condition, ? > bsuv ge v v min where v cc is the ic voltage supply, v f is bootstrap diode forward voltage, v ceon is emitter-collector voltage of low side igbt, and v bsuv- is the high-side supply undervoltage negative going threshold. now we must consider the influencing factors contributing v bs to decrease: ? igbt turn on required gate charge ( q g ), ? igbt gate-source leakage current ( i lk_ge ), ? floating section quiescent current ( i qbs ), ? floating section leakage current ( i lk ), ? bootstrap diode leakage current ( i lk_diode ), ? desat diode bias when on ( i ds ), ? charge required by the internal level shifters ( q ls ); typical 20 nc, ? bootstrap capacitor leakage current ( i lk_cap ), ? high side on time ( t hon ). i lk_cap is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. it is strongly recommend using at least one low esr ceramic capacitor (paralleling electrolytic and low esr ceramic may result in an efficient solution). then we have: + + + + = qbs ge lk ls g tot i i q q q _ ( hon ds cap lk diode lk lk t i i i i ? + + + + ? ) _ _ the minimum size of bootstrap capacitor is: bs tot boot v q c ? = min an example follows using ir2214ss or ir22141ss: a) using a 25 a @ 125 c 1200 v igbt (irgp30b120kd): ? i qbs = 800 a (datasheet ir2214); ? i lk = 50 a (see static electrical characteristics) ; ? q ls = 20 nc ? q g = 160 nc (datasheet irgp30b120kd); ? i lk_ge = 100 na (datasheet irgp30b120kd); ? i lk_diode = 100 a (reverse recovery <100 ns); ? i lk_cap = 0 (neglected for ceramic capacitor); ? i ds- = 150 a (see static electrical characteristics); ? t hon = 100 s. and: ? v cc = 15 v ? v f = 1 v ? v ceonmax = 3.1 v ? v gemin = 10.5 v the maximum voltage drop ? v bs becomes = ? ? ? ? ceon ge f cc bs v v v v v min and the bootstrap capacitor is: nf v nc c boot 725 4.0 290 = notice: v cc has been chosen to be 15 v. some igbts may require a higher supply to work correctly with the bootstrap technique. also v cc variations must be accounted in the above formulas.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 17 2.3 some important considerations voltage ripple: there are three different cases to consider (refer to fig. 19). i load < 0 a; the load current flows in the low side igbt (resulting in v ceon ). ceon f cc bs v v v v ? ? = in this case we have the lowest value for v bs . this represents the worst case for the bootstrap capacit or sizing. when the igbt is turned off, the v s node is pushed up by the load current until the high side freewheeling diode is forwarded biased. i load = 0 a; the igbt is not loaded while being on and v ce can be neglected f cc bs v v v ? = i load > 0 a; the load current flows through the freewheeling diode fp f cc bs v v v v + ? = in this case we have the highest value for v bs . turning on the high side igbt, i load flows into it and v s is pulled up. to minimize the risk of undervoltage, t he bootstrap capacitor should be sized according to th e i load < 0 a case. bootstrap resistor: a resistor (r boot ) is placed in series with the bootstrap diode (see fig. 19) in order to limit the current when the bootstrap capacitor is initial ly charged. we suggest not exceeding 10 to avoid increasing the v bs time-constant. the minimum on time for charging the bootstrap capacitor or for refresh ing its charge must be verified against this time-constant. bootstrap capacitor: for high t hon designs where an electrolytic capacitor is used, its esr must be considered. this parasitic resistance forms a voltag e divider with r boot , which generats a voltage step on v bs at the first charge of bootstrap capacitor. the vol tage step and the related speed (dv bs /dt) should be limited. as a general rule, esr should meet the following constraint. a parallel combination of a small ceramic capacitor and a large electrolytic capacitor is normally the best compromise, the first capacitor posses a fast time constant and limits the dv bs /dt by reducing the equivalent resistance. the second capacitor provide s a large capacitance to maintain the v bs voltage drop within the desired ? v bs . bootstrap diode: the diode must have a bv > 600 v or 1200 v and a fast recovery time (t rr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to v cc supply. 2.4 gate resistances the switching speed of the output transistor can be controlled by properly sizing the resistors control ling the turn-on and turn-off gate currents. the following se ction provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver ( r drp and r drn ). the example shown uses igbt power transistors and figure 20 shows the nomenclature used in the followi ng paragraphs. in addition, v ge * indicates the plateau voltage, q gc and q ge indicate the gate to collector and gate to emitter charge respectively. v ge * 10% t 1 ,q ge c resoff c reson v ce i c v ge c res 10% 90% c res t don v ge dv/dt i c t 2 ,q gc t,q t r t sw figure 20: nomenclature 2.5 sizing the turn-on gate resistor switching-time: for the matters of the calculation included hereafter, the switching time t sw is defined as the time spent to reach the end of the plateau voltage (a total q gc + q ge has been provided to the igbt gate). to obtain the desired switching time th e gate resistance can be sized starting from q ge and q gc , vcc , v ge * (see fig. 21): sw ge gc avg t q q i + = and avg ge tot i v vcc r * ? =
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 18 vcc/vb r drp r gon c res com/vs i avg figure 21: r gon sizing where gon drp tot r r r + = r gon = gate on-resistor r drp = driver equivalent on-resistance r drp is approximately given by ? ?? ? ?? ? > ? + = + + + 1 1 1 1 2 1 1 on sw o on sw sw on sw o on sw o drp t t for i vcc t t for t t t i vcc t t i vcc r (i o1+ ,i o2+ and t on1 from ?static electrical characteristics?). table 1 reports the gate resistance size for two commonly used igbts (calculation made using typical datasheet values and assuming v cc = 15 v). output voltage slope: the turn-on gate resistor r gon can be sized to control the output slope (dv out /dt). while the output voltage has a non- linear behaviour, the maximum output slope can be approximated by: resoff avg out c i dt dv = inserting the expression yielding i avg and rearranging: dt dv c v vcc r out resoff ge tot ? ? = * as an example, table 2 shows the sizing of gate resistance to get dv out /dt= 5 v/ns when using two popular igbts (typical datasheet values are used an d v cc = 15 v is assumed). notice : turn on time must be lower than t bl to avoid improper desaturation detection and ssd triggering. 2.6 sizing the turn-off gate resistor the worst case in sizing the turn-off resistor r goff is when the collector of the igbt in the off state is forced to commutate by an external event (e.g., the turn-o n of the companion igbt). in this case the dv/dt of the output node induces a parasitic current through c resoff flowing in r goff and r drn (see fig. 22). if the voltage drop at the gate exceeds the threshold voltage of t he igbt, the device may self turn on, causing large oscillation and relevant cross conduction. off hs turning on on dv/dt r goff c resoff r drn c ies figure 22: r goff sizing: current path when low side is off and high side turns on the transfer function between the igbt collector and the igbt gate then becomes: ) ( ) ( 1 ) ( ies resoff drn goff resoff drn goff de ge c c r r s c r r s v v + ? + ? + ? + ? = which yields to a high pass filter with a pole at: ) ( ) ( 1 /1 ies resoff drn goff c c r r + ? + = as a result, when is faster than the collector rise time (to be verified after calculation) the transfer fun ction can be approximated by: resoff drn goff de ge c r r s v v ? + ? = ) ( so that dt dv c r r v de resoff drn goff ge ? ? + = ) ( in the time domain. then the condition: ( ) dt dv c r r v v out resoff drn goff ge th ? + = > must be verified to avoid spurious turn on. rearranging the equation yields: drn resoff th goff r dt dv c v r ? ? < r drn is approximately given by
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 19 ? = o drn i vcc r in any case, the worst condition for unwanted turn on is with very fast steps on the igbt collector. in that case, the collector to gate transfer functi on can be approximated with the capacitor divider: ) ( ies resoff resoff de ge c c c v v + ? = which is driven only by igbt characteristics. as an example, table 3 reports r goff (calculated with the above mentioned disequation) for two popular igbts to withstand dv out /dt = 5 v/ns . notice: the above-described equations are intended to approximate a way to size the gate resistance. a more accurate sizing may provide more precise devic e and pcb (parasitic) modelling. igbt qge qgc vge* tsw iavg rtot rgon std commercial value tsw irgp30b120k(d) 19 nc 82 nc 9 v 400 ns 0.25 a 24 rtot - rdrp = 12.7 10 420 ns irg4ph30k(d) 10 nc 20 nc 9 v 200 ns 0.15 a 40 rtot - rdrp = 32.5 33 202 ns table 1: t sw driven r gon sizing igbt qge qgc vge* cresoff rtot rgon std commercial value dvout/dt irgp30b120k(d) 19 nc 82 nc 9 v 85 pf 14 rtot - rdrp = 6.5 8.2 4.5 v/ns irg4ph30k(d) 10 nc 20 nc 9 v 14 pf 85 rtot - rdrp = 78 82 5 v/ns table 2: dv out /dt driven r gon sizing igbt vth(min) cresoff rgoff irgp30b120k(d) 4 85 pf rgoff 4 irg4ph30k(d) 3 14 pf rgoff 35 table 3: r goff sizing
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 20 3 pcb layout tips 3.1 distance from high to low voltage the ir2x14x pinout maximizes the distance between floating (from dc- to dc+) and low voltage pins. it ?s strongly recommended to place components tied to floating voltage on the high voltage side of device (v b , v s side) while the other components are placed on the opposite side. 3.2 ground plane to minimize noise coupling, the ground plane must no t be placed under or near the high voltage floating s ide. 3.3 gate drive loops current loops behave like antennas and are able to receive and transmit em noise. in order to reduce t he em coupling and improve the power switch turn on/of f performances, gate drive loops must be reduced as much as possible. figure 23 shows the high and low side gate loops. moreover, current can be injected inside the gate d rive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-inductance of the g ate loop contributes to developing a voltage across the gate-emitter, increasing the possibility of self tu rn-on. for this reason, it is strongly recommended to place the three gate resistances close together and to minimi ze the loop area (see fig. 23). gate resistance vs/com vb/ vcc h/lop h/lon ssdh/l v ge gate drive loop c gc i gc figure 23: gate drive loop 3.4 supply capacitors the ir2x14x output stages are able to quickly turn o n an igbt, with up to 2 a of output current. the supply capacitors must be placed as close as possible to t he device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/resistance. 3.5 routing and placement example figure 24 shows one of the possible layout solutions using a 3 layer pcb. this example takes into account all the previous considerations. placement and rout ing for supply capacitors and gate resistances in the h igh and low voltage side minimize the supply path loop and the gate drive loop. the bootstrap diode is placed under the device to have the cathode as close as possible to the bootstrap capacitor and the anode far from high voltage and close to v cc . r2 r3 r4 r5 r6 r7 c2 d3 d2 ir2214 v gh v gl dc+ phase a) top layer d1 r1 c1 v eh v el v cc b) bottom layer c) ground plane figure 24: layout example information below refers to fig. 24: bootstrap section: r1, c1, d1 high side gate: r2, r3, r4 high side desat: d2 low side supply: c2 low side gate: r5, r6, r7 low side desat: d3
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 21 figures 25-83 provide information on the experimenta l performance of the ir2114/IR2214SSPBF hvic. the li ne plotted in each figure is generated from actual lab data. a large number of individual samples from multiple w afer lots were tested at three temperatures (-40 oc, 25 oc, and 12 5 oc) in order to generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data point at each of the tested temperatures) that hav e been connected together to illustrate the understood trend. the in dividual data points on the curve were determined b y calculating the averaged experimental value of the parameter (for a given temperature). 9.95 10.00 10.05 10.10 10.15 10.20 10.25 10.30 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) figure 25. v ccuv+ threshold vs. temperature exp. 0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs quiescent current (ua) figure 29. v bs quiescent current vs. temperature exp. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc quiescent current (ma) figure 30. v cc quiescent current vs. temperature exp. 10.00 10.05 10.10 10.15 10.20 10.25 10.30 10.35 10.40 10.45 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv+ threshold threshold (v) figure 27. v bsuv+ threshold vs. temperature exp. 9.25 9.30 9.35 9.40 9.45 9.50 9.55 9.60 9.65 9.70 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv- thresholdthreshold (v) figure 28. v bsuv- threshold vs. temperature exp. 9.15 9.20 9.25 9.30 9.35 9.40 9.45 9.50 9.55 9.60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv- threshold (v) figure 26. v ccuv- threshold vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 22 1.10 1.50 1.90 2.30 2.70 -50 -25 0 25 50 75 100 125 temperature ( o c) v ih logic input voltage (v) figure 31. v ih logic input voltage vs. temperature exp. 0.90 1.20 1.50 1.80 2.10 -50 -25 0 25 50 75 100 125 temperature ( o c) v il logic input voltage (v) figure 32. v il logic input voltage vs. temperature exp. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ihss hin logic input hysteresis (v) figure 33. v ihss hin logic input hysteresis vs. temperature exp. 1.00 1.30 1.60 1.90 2.20 -50 -25 0 25 50 75 100 125 temperature ( o c) lin logic "1" input voltage (v) figure 34. lin logic "1" input voltage vs. tempera ture exp. 0.70 1.00 1.30 1.60 1.90 -50 -25 0 25 50 75 100 125 temperature ( o c) lin logic "0" input voltage (v) figure 35. lin logic "0" input voltage vs. tempera ture exp. 0.10 0.30 0.50 0.70 0.90 -50 -25 0 25 50 75 100 125 temperature ( o c) v ihss lin logic input hysteresis (v) figure 36. v ihss lin logic input hysteresis vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 23 1.10 1.40 1.70 2.00 2.30 -50 -25 0 25 50 75 100 125 temperature ( o c) v ih fltclr logic input voltage (v) figure 37. v ih fltclr logic input voltage vs. temperature exp. 0.80 1.10 1.40 1.70 -50 -25 0 25 50 75 100 125 temperature ( o c) v il fltclr logic input hysteresis (v) figure 38. v il fltclr logic input voltage vs. temperature exp. 0.20 0.30 0.40 0.50 0.60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ihss fltclr logic input hysteresis (v) figure 39. v ihss fltclr logic input hysteresis vs. temperature exp. 0.50 0.90 1.30 1.70 2.10 -50 -25 0 25 50 75 100 125 temperature ( o c) v ih sd logic input voltage (v) figure 40. v ih sd logic input voltage vs. temperature exp. 0.50 0.90 1.30 1.70 2.10 -50 -25 0 25 50 75 100 125 temperature ( o c) v il sd logic input voltage (v) figure 41. v il sd logic input voltage vs. temperature exp. 0.20 0.30 0.40 0.50 0.60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ihss sd logic input hysteresis (v) figure 42. v ihss sd logic input hysteresis vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 24 0.80 1.20 1.60 2.00 2.40 -50 -25 0 25 50 75 100 125 temperature ( o c) v ih syflt logic input voltage (v) figure 43. v ih syflt logic input voltage vs. temperature exp. 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ol lo (mv) figure 46. v ol lo vs. temperature exp. 200 375 550 725 900 -50 -25 0 25 50 75 100 125 temperature ( o c) v oh lo (mv) figure 47. v oh lo vs. temperature exp. 25 35 45 55 65 -50 -25 0 25 50 75 100 125 temperature ( o c) v ol ho (mv) figure 48. v ol ho vs. temperature exp. 0.80 1.20 1.60 2.00 2.40 -50 -25 0 25 50 75 100 125 temperature ( o c) v il syflt logic input voltage (v) figure 44. v il syflt logic input voltage vs. temperature exp. 0.20 0.30 0.40 0.50 0.60 -50 -25 0 25 50 75 100 125 temperature ( o c) v ihss syflt logic input hysteresis (v) figure 45. v ihss syflt logic input hysteresis vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 25 200 375 550 725 900 -50 -25 0 25 50 75 100 125 temperature ( o c) v oh ho (mv) figure 49. v oh ho vs. temperature exp. 5 6 7 8 9 -50 -25 0 25 50 75 100 125 temperature ( o c) v dsh+ dsh input voltage (v) figure 50. v dsh+ dsh input voltage vs. temperature exp. 7 8 8 9 9 -50 -25 0 25 50 75 100 125 temperature ( o c) v dsl+ dsl input voltage (v) figure 51. v dsl+ dsl input voltage vs. temperature exp. 5.50 6.20 6.90 7.60 8.30 -50 -25 0 25 50 75 100 125 temperature ( o c) v dsh- dsh input voltage (v) figure 52. v dsh- dsh input voltage vs. temperature exp. 6.00 6.50 7.00 7.50 8.00 -50 -25 0 25 50 75 100 125 temperature ( o c) v dsl- dsl input voltage (v) figure 53. v dsl- dsl input voltage vs. temperature exp. 30 45 60 75 90 -50 -25 0 25 50 75 100 125 temperature ( o c) fault/sd open drain resistance ( ) figure 54. fault/sd open drain resistance vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 26 30 55 80 105 130 -50 -25 0 25 50 75 100 125 temperature ( o c) sy_flt open drain resistance ( ) figure 55. sy_flt open drain resistance vs. tempera ture exp. 250 310 370 430 490 -50 -25 0 25 50 75 100 125 temperature ( o c) dtl off deadtime (ns) figure 56. dtl off deadtime vs. temperature exp. 250 310 370 430 490 -50 -25 0 25 50 75 100 125 temperature ( o c) dth off deadtime (ns) figure 57. dth off deadtime vs. temperature exp. 300 420 540 660 780 -50 -25 0 25 50 75 100 125 temperature ( o c) tonh propagation delay (ns) figure 58. tonh propagation delay vs. temperature exp. 300 420 540 660 780 -50 -25 0 25 50 75 100 125 temperature ( o c) toffh propagation delay (ns) figure 59. toffh propagation delay vs. temperature exp. 12 16 20 24 28 32 -50 -25 0 25 50 75 100 125 temperature ( o c) trh turn on rise time (ns) figure 60. trh turn on rise time vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 27 6 9 12 15 18 -50 -25 0 25 50 75 100 125 temperature ( o c) tfh turn off fall time (ns) ) figure 61. tfh turn off fall time vs. temperature exp. 300 420 540 660 780 -50 -25 0 25 50 75 100 125 temperature ( o c) tonl propagation delay (ns) figure 62. tonl propagation delay vs. temperature exp. 300 420 540 660 780 -50 -25 0 25 50 75 100 125 temperature ( o c) toffl propagation delay (ns) figure 63. toffl propagation delay vs. temperature exp. 12 19 26 33 40 -50 -25 0 25 50 75 100 125 temperature ( o c) trl turn on rise time (ns) figure 64. trl turn on rise time vs. temperature exp. 4 8 12 16 20 -50 -25 0 25 50 75 100 125 temperature ( o c) tfl turn off fall time (ns) figure 65. tfl turn off fall time vs. temperature exp. 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) t dsat1 (us) figure 66. t dsat1 vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 28 1 2 2 3 3 -50 -25 0 25 50 75 100 125 temperature ( o c) t dsat2 (us) figure 67. t dsat2 vs. temperature exp. 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) t dsat3 (us) figure 68. t dsat3 vs. temperature exp. 0.50 1.50 2.50 3.50 4.50 -50 -25 0 25 50 75 100 125 temperature ( o c) t dsat4 (us) figure 69. t dsat4 vs. temperature exp. 5 8 11 14 17 -50 -25 0 25 50 75 100 125 temperature ( o c) t ssh (us) figure 70. t ssh vs. temperature exp. 5 8 11 14 17 -50 -25 0 25 50 75 100 125 temperature ( o c) t ssl (us) figure 71. t ssl vs. temperature exp. 0.40 0.75 1.10 1.45 1.80 -50 -25 0 25 50 75 100 125 temperature ( o c) io2+h sc pulsed current (a) figure 72. io2+h sc pulsed current vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 29 0.40 0.75 1.10 1.45 1.80 -50 -25 0 25 50 75 100 125 temperature ( o c) io2+l sc pulsed current (a) figure 73. io2+l sc pulsed current vs. temperature exp. 1.45 1.90 2.35 2.80 3.25 -50 -25 0 25 50 75 100 125 temperature ( o c) io-h sc pulsed current (a) figure 74. io-h sc pulsed current vs. temperature exp. 1.25 1.70 2.15 2.60 3.05 3.50 -50 -25 0 25 50 75 100 125 temperature ( o c) io-l sc pulsed current (a) figure 75. io-l sc pulsed current vs. temperature exp. 100 300 500 700 900 -50 -25 0 25 50 75 100 125 temperature ( o c) t on1h (ns) figure 76. t on1h vs. temperature exp. 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) t on1l (ns) figure 77. t on1l vs. temperature exp. 1.00 1.50 2.00 2.50 3.00 -50 -25 0 25 50 75 100 125 temperature ( o c) io1+h sc pulsed current (a) figure 78. io1+h sc pulsed current vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 30 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) io1+l sc pulsed current (ns) figure 79. io1+l sc pulsed current vs. temperature exp. 100 300 500 700 900 -50 -25 0 25 50 75 100 125 temperature ( o c) i hin+ logic "1" input bias current (ua) figure 80. i hin+ logic "1" input bias current vs. temperature exp. -0.28 -0.23 -0.18 -0.13 -0.08 -0.03 0.02 -50 -25 0 25 50 75 100 125 temperature ( o c) i hin- logic "0" input bias current (ua) figure 81. i hin- logic "0" input bias currentvs. temperature exp. 100 300 500 700 900 -50 -25 0 25 50 75 100 125 temperature ( o c) i lin+ logic "1" input bias current (ua) figure 82. i lin+ logic "1" input bias current vs. temperature exp. -0.28 -0.23 -0.18 -0.13 -0.08 -0.03 0.02 -50 -25 0 25 50 75 100 125 temperature ( o c) i lin- logic "0" input bias current (ua) figure 83. i lin- logic "0" input bias current vs. temperature exp.
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 31 case outline
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 32 carrier tape dimension for 24ssop:2000 units per re el code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 8.30 8.50 0.326 0.334 f 8.50 8.70 0.334 0.342 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 24ssop code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c
ir2114/IR2214SSPBF www.irf.com ? 2009 international rectifier 33 worldwide headquarters: 233 kansas street, el segundo, ca 90245 tel: (310) 252-7105 thi s part has been qualified per industrial level http://www.irf.com data and specifications subject to change without notice. 5/18/2006 order information 24-lead ssop ir2114sspbf 24-lead ssop IR2214SSPBF 24-lead ssop tape & reel ir2114sspbf 24-lead ssop tape & reel IR2214SSPBF

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